1. Field of the Invention
The present invention relates generally to command processing applications in high bandwidth memory systems.
2. Cross Reference to Other Applications
The following pending application is owned by the assignee of the present application, and its contents are hereby incorporated by reference:
Ser. No. 09/132,158 filed Aug. 10, 1998, invented by Gustavson et. al and entitled, MEMORY SYSTEM HAVING SYNCHRONOUS-LINK DRAM (SLDRAM) DEVICES AND CONTROLLER.
3. Description of the Related Art
The evolution of the dynamic random access memories used in computer systems has been driven by ever-increasing speed requirements mainly dictated by the microprocessor industry. Dynamic random access memories (DRAMs) have generally been the predominant memories used for computers due to their optimized storage capabilities. This large storage capability comes with the price of slower access time and the requirement for more complicated interaction between memories and microprocessors/microcontrollers than in the case of say static random access memories (SRAMS) or non-volatile memories.
In an attempt to address this speed deficiency, DRAM design has implemented various major improvements, all of which are well documented. Most recently, the transition from Fast Page Mode (FPM) DRAM to Extended Data Out (EDO) DRAMs and synchronous DRAMs (SDRAMS) has been predominant. Further speed increases have been achieved with double data rate (DDR) SDRAM, which synchronizes data transfers on both clock edges. New protocol based memory interfaces have recently been developed to further increase the bandwidth and operating frequencies of synchronous memories.
As the complexity of these memories has increased, the associated control systems responsible for internally managing the operation of the memories have also become more complex. These command-driven control systems internally must typically process a stream of commands or instructions that overlap in execution time and have programmable latency (time from receipt of command to first control outputs asserted in response). Programmable latency is desirable in such systems in order to allow the memory controller to schedule the use of shared data, address or control buses for optimum usage. Since the processing of two or more commands may be required to occur simultaneously, many control systems implement multiple functional units operating in parallel. The minimum latency of the control system is therefore limited by the need to (i) decode the command control field(s), (ii) determine the programmed latency associated with the identified command, and (iii) issue the command to a number of parallel functional units before the first control output action can be determined for use by the memory.
A conventional implementation of such a memory system control block comprises a single front end decoding block which decodes external commands and issues internal commands to multiple identical functional elements capable of operating in parallel. The minimum latency therefore cannot be shorter than the time it takes to decode the command in the front end block plus the time required to issue the command to a parallel functional unit, and finally, the time that the functional unit takes to initialize and issue its first control action. The common approach to reducing the minimum latency described above is by replicating the command decoding logic within each parallel functional unit and feeding the command stream to all parallel functional units simultaneously to eliminate the issue and initialization delay. This advantage comes with the cost of a large increase in overall logic complexity, redundant logic, and increased power consumption. As frequency and bandwidth requirements increase, there is a need for a memory system control block which makes optimum use of area and power consumption and which can process commands with a reduced minimum latency than previously achieved in the prior art.